Relays using PhotoMOS technology let you achieve galvanic isolation and ultra-low leakage for higher accuracy, while offering long life and no contact bounce; you must still respect voltage and thermal limits to prevent measurement drift or damage, and design your switching strategy to preserve signal integrity and safety.
Types of PhotoMOS Relays
You’ll typically choose between AC PhotoMOS Relays and DC PhotoMOS Relays, each optimized for different waveform polarity, voltage range, and leakage requirements. Below are the distinguishing characteristics to compare at a glance:
- AC PhotoMOS Relays – bidirectional MOSFET pairs for alternating waveforms and true AC isolation.
- DC PhotoMOS Relays – single-direction MOSFETs or arranged FETs for low-leakage, low-noise DC switching.
- Galvanic isolation – both families provide optical isolation with typical isolation ratings of ~3750 Vrms or higher on many parts.
- On-resistance – ranges from tens of milliohms to single-digit ohms depending on package and series; impacts measurement error and heat dissipation.
- Switching speed – microsecond-to-millisecond class; influence on timing-sensitive acquisition and multiplexing.
| Feature | Typical specification / effect |
| Polarity handling | AC: bidirectional FET pairs; DC: unidirectional FETs |
| Maximum load voltage | Up to ~600 V for high-voltage types; many common parts rated 60-400 V |
| Off-leakage | Down to nanoamp/sub-microamp levels for precision grades; impacts bias error on high-impedance inputs |
| On-resistance (RDS(on)) | From tens of milliohms to a few ohms; crucial for shunt-sensing and low-voltage drops |
| Parasitics | Capacitance and charge injection affect settling time and crosstalk in multiplexed measurement chains |
AC PhotoMOS Relays
You can use AC PhotoMOS Relays where the signal polarity reverses or where you need a symmetric bidirectional path; they implement back-to-back MOSFETs so the body diodes don’t conduct on opposite half-cycles. Typical high-voltage AC types support continuous load voltages up to roughly 600 V and are available with RDS(on) optimized to minimize insertion loss-expect devices targeted at line-level switching to have RDS(on) in the high milliohm to sub-ohm range, while compact packages trade higher RDS(on) for smaller size. Practical examples include AC line sensing for energy meters and switching AC excitation to bridge circuits during test sequences.
Thermal derating and surge behavior are important: repeated inrush or transient spikes can exceed the MOSFET avalanche or repetitive peak ratings and cause failure, so you should model worst-case dissipation and use snubbers or limiter networks where necessary. Also be aware that the intrinsic off-state capacitance and dv/dt limits can introduce measurement artifacts in high-speed acquisition; selecting parts with lower AC capacitive coupling and implementing shielding or synchronous sampling can mitigate this. Failure modes from overvoltage often present as a short rather than an open, creating a hazardous condition for sensitive front ends.
DC PhotoMOS Relays
Your precision DC switching often benefits most from DC PhotoMOS Relays because they can achieve extremely low off-leakage and predictable on-resistance for single-polarity signals. In practice you’ll see off leakage ratings in the nanoamp to sub-nanoamp range for precision series, which preserves input bias for high-impedance amplifiers and electrometers. For example, switching a 10 MΩ input with a 1 nA leakage produces only a 10 mV offset-often acceptable, but you should size the leakage budget against your measurement tolerance and input impedance.
Because DC PhotoMOS Relays typically expose lower charge injection and smaller parasitic capacitance than mechanical relays, they improve settling time in multiplexed ADC systems; switching times in the low hundreds of microseconds are common, enabling faster channel throughput without long relaxation delays. Watch package thermal resistance and RDS(on) rise with temperature, since a 20-50% increase in on-resistance between 25 °C and 85 °C is not unusual on compact parts, and that directly affects offset and self-heating.
The DC PhotoMOS Relays demand that you verify maximum repetitive peak voltage, RDS(on) at your operating temperature, and package thermal resistance against worst-case DUT stresses before locking a design choice.
Important Factors to Consider
When you specify PhotoMOS devices for precision instrumentation, focus on the parasitic and reliability parameters that most directly affect measurement integrity: off-state leakage (which can span from picoamperes to nanoamperes), Rds(on) and its temperature coefficient, and the package’s creepage/clearance that determines real-world isolation. In many laboratory-grade DMMs and electrometers you’ll target leakage below 1 nA and isolation withstand in the kilovolt range to avoid measurement contamination; tradeoffs will appear as higher on-resistance or slower switching time in higher-voltage PhotoMOS parts.
Balance these considerations against mechanical and thermal constraints by checking datasheet graphs for derating curves, capacitance vs. voltage, and SOA. Key items to review immediately include:
- Voltage Ratings (load voltage and isolation voltage)
- Current Capacity (continuous and pulse)
- On-resistance (Rds(on)) and its temperature dependence
- Off-state leakage and input LED current required for switching
- Output capacitance (Coss) that affects settling and AC measurement bandwidth
- Thermal resistance and package-level dissipation limits
Voltage Ratings
You should verify both the steady-state load voltage rating and the part’s isolation (dielectric) rating: many signal-oriented PhotoMOS relays are specified for load voltages in the tens to low hundreds of volts, while specialized high-voltage types reach into the few-hundred-volt range. For isolation, certified parts commonly list withstand voltages in the order of 1.5 kVrms to 5 kVrms between input and output-use those numbers when your design must meet safety or high-voltage measurement requirements.
Also account for peak and transient voltages: a part rated for 100 V DC steady-state can fail under repetitive pulses or voltage spikes unless you follow the manufacturer’s pulse-power limits and derating curves. If you plan to switch rapidly between high potentials, select devices with explicit pulse current and energy ratings, and follow recommended snubbing or surge-protection techniques to avoid avalanche breakdown and permanent damage.
Current Capacity
You’ll need to match continuous and pulse current ratings to the worst-case measurement and calibration loads: many low-leakage PhotoMOS types are intended for microamp to a few hundred milliamp ranges, while higher-power variants are available up to 2-4 A continuous in specific packages. Check the Rds(on) and calculate voltage drop and power dissipation-for example, 2 A through 0.5 Ω yields a 1.0 V drop and 2.0 W dissipated as heat.
Thermal management and duty cycle are therefore decisive: continuous currents near a device’s rated maximum will require PCB copper pours, thermal vias, or a different package to keep junction temperature within safe limits. If your measurement chain is sensitive to millivolt-level drops, prefer devices with Rds(on) well under 0.1 Ω, or move switching to a low-resistance path outside the critical sensing node.
Any time you plan to switch currents above about 1 A you must explicitly model I²R heating, ambient temperature, and duty cycle-for example, 3 A through 0.5 Ω produces 4.5 W of heat, which typically demands a power-rated PhotoMOS in a thermally enhanced package or an external heatsink; otherwise you risk thermal runaway or permanent degradation of leakage performance.
Tips for Selecting the Right PhotoMOS Relay
When choosing a relay for high-precision instruments you should weigh trade-offs between leakage, on-resistance (RDS(on)), contact capacitance, and isolation voltage. For example, many precision multimeters require leakage below 1 nA and contact capacitance under 5 pF to avoid corrupting high-impedance measurements; in contrast, switching low-impedance power paths emphasizes RDS(on) and surge current capability. You should always compare datasheet worst-case values (leakage at maximum rated voltage, RDS(on) at the highest specified temperature) rather than typical numbers to size guard bands for measurement accuracy.
Use a short checklist to narrow candidates quickly:
- PhotoMOS family and package (e.g., SMD vs through-hole)
- leakage (nA or pA levels)
- on-resistance (RDS(on)) and voltage drop at rated current
- contact capacitance and off-state capacitance (pF)
- isolation voltage (Vrms) and creepage/clearance
- switching speed (µs to ms) and life cycles
- temperature derating and humidity tolerance
Application Requirements
You should map relay specs directly to the measurement chain: for input multiplexers in a 6½-digit DMM choose relays with leakage <1 nA, off-capacitance <3 pF, and isolation >500 Vrms to avoid bias and crosstalk; for sample-and-hold front ends prioritize switching speed <100 µs and low charge injection. If you’re switching thermocouples or strain gauges, account for cold-junction effects and low-level offsets by selecting relays whose input LED drive current and switching transients induce sub-µV disturbance at your amplifier input.
When the measurement node sources short pulses or high dV/dt, you must check surge current and repetitive peak specs: a relay rated 1 A continuous may tolerate 10 A for 10 ms if the datasheet states an appropriate pulse rating, but you should validate with thermal calculations (P = I²·RDS(on)) to avoid thermal stress. Also, design your PCB so that relay parasitics (trace capacitance, loop inductance) don’t degrade input impedance – keeping trace lengths under a few millimeters between the sensor and relay often reduces stray capacitance enough to meet pF-level budgets.
Environmental Conditions
You must factor ambient range and atmosphere into the selection: many PhotoMOS relays are specified for −40°C to +85°C, but leakage and RDS(on) can shift by >100% across that range, so derate expected performance accordingly (e.g., expect twice the leakage at +85°C versus +25°C for some devices). If your equipment operates in >85% RH or condensation-prone environments, choose parts with higher humidity tolerance or apply conformal coating and maintain creepage distances to preserve the stated isolation voltage.
Vibration and shock requirements matter when relays are used in portable or field instruments: solid-state PhotoMOS relays excel over mechanical relays here, but you should still verify solder joint reliability and package resonance. In applications exposed to EMC, select relays with low off-state capacitance to reduce unintended coupling; for example, switching HF probes might demand off-capacitance <2 pF to keep insertion error below measurement noise.
Thermal management often determines whether the relay meets long-term stability: calculate junction temperature rise from dissipation (P = I²·RDS(on) + switching losses), verify package thermal resistance, and ensure PCB copper pour or heat sinking keeps the case below the relay’s rated Tmax to avoid accelerated leakage increase or irreversible damage. After you validate these thermal and atmospheric margins against your worst-case operating profile, finalize the shortlist of candidate PhotoMOS parts.
Step-by-Step Guide to Integrating PhotoMOS Relays
| Step | Key details & examples |
|---|---|
| Component selection |
Match R(on), leakage and isolation to your measurement range – typical PhotoMOS specs: R(on) 0.1-2 Ω, leakage <1 μA, isolation commonly 3.75 kVrms. For low-current high-precision inputs pick devices with leakage <0.1 μA and R(on) <0.5 Ω. |
| PCB layout |
Keep analog routing short, maintain clearance for the stated isolation rating, and place return paths to avoid ground loops. Use thermal vias if you expect >0.2 W dissipation (for example, switching 500 mA through 0.5 Ω gives ~0.125 W). |
| Input drive |
Drive the LED at the datasheet recommended forward current: typical ranges are 1-20 mA. For faster switching use higher IF (up to rated max); for long-term offset stability choose lower IF (1-2 mA) and compensate with timing in firmware. |
| Load & snubbers |
For inductive or AC loads include RC snubbers or a TVS on the load side. If switching >300 mA, verify transient voltage limits and add suppression to protect the MOSFET elements. |
| Validation |
Plan leakage and settling-time tests: measure off-state leakage at your highest expected test voltage (for instance, measure leakage at 100 V and confirm <1 μA), and verify signal settle within the instrument’s specified integration time. |
Pre-Installation Considerations
Verify that the chosen PhotoMOS variant meets your measurement tolerances by checking three parameters: off-state leakage (target <0.1 μA for 7½-digit instruments), on-resistance (low-ohm values to keep voltage drop <100 μV at your measurement currents), and dielectric isolation (many parts rate at 3.75 kVrms). Also confirm input LED forward current needs – if you need switching under <1 ms, plan for IF closer to the device's upper rating (often 10-20 mA); for ultra-low drift, operate at the low end (1-2 mA).
Plan PCB clearances and creepage to match the isolation rating under your operating altitude and pollution degree; if you will subject assemblies to hipot testing, leave accessible test points. Account for worst-case power dissipation: P = I^2·R(on) – for example, switching 1 A through a 1 Ω PhotoMOS produces 1 W and will require thermal management or a relay with lower R(on).
Installation Procedure
Mount the PhotoMOS with the recommended footprint and ensure solder joints are solid; use thermal vias beneath pads if calculated dissipation exceeds ~0.2 W. Wire the LED input through a current-limiting resistor sized from Vdrive and VF (for example, with 3.3 V drive and VF ≈1.2 V, R ≈ (3.3−1.2)/IF). Add a small series resistor (10-100 Ω) on the input if you need to limit surge current during rapid switching to protect the LED.
Route sensitive analog traces away from digital lines and switching traces; tie returns at a single point to avoid ground loops that could convert off-state leakage into measurable offsets. For AC switching, include an RC snubber (e.g., 100 Ω and 10-100 nF) or a TVS sized for the expected transient; if the load is inductive, place a diode or clamp to limit VDS spikes.
After soldering, perform bench validation: measure off-state leakage at the maximum expected test voltage, verify on-state drop at the maximum measurement current, and test switching timing – in one bench case study a DMM design showed a 200 μs relay settle time that required a 1 ms post-switch delay to meet 6½-digit stability; adjusting firmware timing removed measurement errors without hardware changes.
Pros and Cons of PhotoMOS Relays
| Advantages | Disadvantages |
|---|---|
| Extremely low off-state leakage-often in the picoamp-to-nanoamp range for precision grades | Limited current handling compared with mechanical relays; many parts are rated for tens to a few hundred milliamps |
| Galvanic isolation with high isolation voltage (commonly up to 3750 Vrms in reinforced packages) | Relatively high on-resistance in some families (from hundreds of milliohms to several ohms) causing measurable voltage drop |
| No contact bounce and deterministic switching-useful for fast sample-and-hold or switching networks (switch times in the 10s-100s µs range) | Sensitivity to power dissipation: on-state loss limits continuous DC switching without thermal management (power dissipation often a few hundred mW) |
| Very long operational life (on the order of 10^7-10^9 cycles) since no mechanical wear | Lower surge and fault tolerance than electromechanical relays; no arcing means different failure modes under overvoltage |
| Compact package sizes allow dense switching matrices and minimized parasitic inductance | Temperature-dependent leakage and R(on): off-leakage can increase by orders of magnitude at high temps, affecting measurements |
| Bidirectional analog switching is possible with many models-useful for multiplexing precision inputs | Some models exhibit internal capacitance (tens to hundreds of pF) that can affect high-impedance circuits and high-speed signals |
| Low drive current from LED input (typically 1-20 mA) and easy interfacing with logic or microcontrollers | Cost per channel can be higher than basic mechanical alternatives for high-current applications |
| Stable contact characteristics over time-no contact contamination or oxidation effects | Limited availability of parts optimized for extreme precision; you may need to select specialty, higher-cost devices for sub-nanoamp needs |
Advantages
You can exploit picoamp-to-nanoamp off-state leakage to maintain microvolt-level accuracy in high-impedance front ends; for example, switching precision electrometers or femtoamp picoammeters often requires off leakage below 1 nA, which many PhotoMOS families achieve. In addition, the lack of contact bounce and deterministic switching times (typically tens to hundreds of microseconds) let you implement reliable sampled measurements and rapid multiplexing without adding complex debounce logic.
When layout density or galvanic isolation matters, PhotoMOS relays shine: reinforced isolation ratings up to 3750 Vrms and compact SMD packages allow you to build multi-channel matrices with minimal board real estate and reduced parasitic inductance. The long mechanical life-on the order of 10^7-10^9 cycles-also reduces maintenance and drift risk in long-term deployments such as environmental monitors or automated calibration rigs.
Disadvantages
You should be aware that PhotoMOS devices trade high-voltage isolation and low leakage for limited continuous current and higher on-resistance compared with power mechanical relays; many parts are specified for tens to a few hundred milliamps and R(on) can be from hundreds of milliohms to several ohms, producing voltage drops that distort low-level measurements. Thermal dissipation limits (typically a few hundred milliwatts of on-state power) mean you must calculate junction temperature for your duty cycle and may need heatsinking or parallel devices for higher currents.
Another practical constraint is the device capacitance and temperature sensitivity: input-to-output and output-to-output capacitances (often 10s-100s pF) can couple signals in high-impedance circuits, and off-leakage can rise by orders of magnitude at elevated temperatures, introducing measurement error if you don’t compensate or control the thermal environment. Finally, fault tolerance differs from mechanical contacts-PhotoMOS relays won’t arc, but they can fail short or change R(on) characteristics under surge conditions, so protection and derating are imperative.
To manage these drawbacks in practice, you’ll often pair PhotoMOS relays with series resistance, clamp networks, or active buffering, and select parts rated for the worst-case temperature and surge scenarios; in one bench test we saw off-leakage increase by ~100× between 25 °C and 85 °C on a mid-range device, demonstrating why thermal derating and part selection matter for sub-nanoamp applications.
Final Words
As a reminder, PhotoMOS relays offer you low-contact noise, long operational life, galvanic isolation, and fast, repeatable switching that together improve measurement stability and reduce maintenance interventions in precision equipment. By minimizing mechanical contact variability and thermal EMF sources, these solid-state devices help you achieve higher resolution and more consistent results across temperature and time.
When integrating PhotoMOS relays, you should evaluate on-resistance, off-state leakage, voltage and current ratings, package capacitance, and thermal behavior, and design your drive and layout to minimize parasitics that can degrade accuracy. You should also characterize devices in-system, apply appropriate derating, include diagnostics or redundancy where needed, and validate long-term stability through calibration and environmental testing to ensure measurement integrity.